Dr. Barlage is currently a Professor in Electrical and Computer Engineering. Prior to joining the University of Alberta, Dr. Barlage was at North Carolina State University where he was among the first to produce an enhancement mode GaN MOSFET. For these efforts, he was recognized by the US National Science Foundation with a CAREER young investigator award. While there he investigated different rare earth metal oxides for use in a MOSFET structure, and co-led a team that demonstrated the first selective area regrowth for source drains in GaN based transistors. His students also produced the highest performing GaN MOSFET with a Schotky barrier source –drain to date, this work received best student paper honors at the International Symposium for Device Research. Prior to NC State, Dr. Barlage was at Intel corporation where he was lab manager for the Novel Device Lab. While there he was part of the team that introduced the first high-k gate dielectric for logic, produced the smallest functional transistor in 2000 (Named to MIT’s TR35 list in 2002 for his contributions to this work) and explored the limits of transistor technology with the triple gate transistor as a manufacturable alternative to nano-wire based electronics. Dr. Barlage received his Ph.D. at the University of Illinois in Urbana Champaign in 1997 focusing on modeling of InGaP/GaAs Hetero-junction Bipolar transistors. During his studies he was also employed by the US Air Force Wright labs Sensors Directorate where he worked on methods to enhance dynamic thermal stability of electronic devices.
Arguably, the transistor has made the biggest impact on human civilization since the development of agriculture. My interests are to further expand the limits of this development through enhanced use of new materials. At the very nano-scale, it involves designing and testing devices and materials to produce a compelling alternative to the best low power device architecture available -- silicon CMOS. At the very large, enhanced use of electronics stands to make great impacts in the power management systems of the future. Under both circumstances, while the size may be much different, the electric fields that are managed are nearly the same. Furthermore, power efficiency is critical to both applications and similar governing physical mechanisms require investigation. The simultaneous investigation of new materials and device architectures requires a rigorous, collaborative and very interdisciplinary approach.
Immediate opportunities exist for the deployment of devices using wide band-gap materials. Current projects include the demonstration of an optimized GaN based enhancement device with re-grown source drain and high-k gate dielectric suitable for high voltage applications >1200V. Other projects involve the defect tolerance in wide band-gap materials such as ZnO a compelling low-cost easily deposited and formed material with potentially large breakdown field and high saturation velocity. While my interests are in the electronics area, Both GaN and ZnO are currently being actively pursued for optical applications and are seen as a potential device material for electronics.
The primary objective of advanced course work is to make the nano-scale more intellectually accessible. Many of the phenomena we use at the nano-scale has no observational analogy. To be an engineer at the nano-scale and address the challenges of the 21st century, one must be able intuition about behaviors at the scale. As current director of the EE450 lab we have assembled a unique collection of equipment (see photo) that will hopefully enhance the next generation of engineer’s ability to comprehend and manipulate the very small for the benefit of mankind.