Architecture of historical and contemporary computer systems, including CPU chips and buses, memory, secondary memory devices, and I/O interfaces. Performance enhancement techniques, including prefetching, pipelining, caching, branch prediction, out-of-order and speculative execution, explicit parallelism, and predication are discussed. The course also includes the data path and control logic at the microarchitecture level; error detection and correction; floating-point number representation and calculation; fast arithmetic circuits; instruction sets and formats; and an overview of alternative and parallel architectures, including RISC/CISC, SIMD/MIMD, shared memory and message passing architectures. Prerequisite: AUCSC 250.