ECE 512 - Digital System Testing and Design for Testability

★ 3 (fi 6)(EITHER, 3-0-0)

Faculty of Engineering

Production testing versus design verification of digital VLSI/ULSI systems. Economics of testing. Defect distributions, yield analysis, and minimum fault coverage requirements. Fault modelling, fault simulation, and automatic test pattern generation. Memory testing. Iddq current-based testing. Design for testability (DFT) rules and strategies. Scan chain based DFT. Built-in self-test (BIST) circuits and architectures. The IEEE JTAG boundary scan and embedded core test standards. Advanced testing topics.

No syllabi

Winter Term 2024

Lectures

Section Capacity Class times Instructor(s)
LECTURE B1
(19060)
12
2024-01-08 - 2024-04-12 (MWF)
10:00 - 10:50
NRE 2-016
Primary Instructor: Bruce Cockburn