ECE 512 - Digital System Testing and Design for Testability

★ 3 (fi 6)(EITHER, 3-0-0)

Faculty of Engineering

Production testing versus design verification of digital VLSI/ULSI systems. Economics of testing. Defect distributions, yield analysis, and minimum fault coverage requirements. Fault modelling, fault simulation, and automatic test pattern generation. Memory testing. Iddq current-based testing. Design for testability (DFT) rules and strategies. Scan chain based DFT. Built-in self-test (BIST) circuits and architectures. The IEEE JTAG boundary scan and embedded core test standards. Advanced testing topics.

Fall Term 2021


LECTURE 800 (57031)
Capacity: 25
2021-09-01 - 2021-12-07
MWF 09:00 - 09:50 (TBD)

Primary Instructor: Bruce Cockburn